1. Field of the Invention
The present invention relates to a wiring board that includes an interlayer connection layer in an insulating substrate, an electronic component embedded substrate, a method of manufacturing a wiring board, and a method of manufacturing an electronic component embedded substrate.
2. Description of the Related Art
Many recent circuit boards are highly dense. Wiring boards that include an interlayer connection layer in an insulating substrate have been proposed as boards on which interconnects can be provided densely.
For example, Japanese Laid-open Patent Publication No. 11-214850 discloses a method of manufacturing a printed board that includes a step of forming an interconnect pattern on the surface of a core material; a step of forming, on the surface of the core material that includes the interconnect pattern, an insulating layer made of organic resin in which an inorganic filler is mixed; a step of selectively forming, in the insulating layer, a connection hole that reaches the interconnect pattern; a step of performing surface roughening by removing the surface of the insulating layer by dry etching; a step of forming, by using vacuum film forming, an electroplating conductive film on the surface of the insulating layer that contains the inorganic filler; and a step of forming a conductive film on the electroplating conductive film by electroplating. The document describes that a printed board having a fine interconnect width and interconnect interval can be formed, with a smaller number of steps.
To cope with the fine interconnect, the via diameter decreases and the aspect ratio (via depth/via diameter) increases. As the aspect ratio increases, it becomes difficult to provide a conductive film stably on the surface of the insulating layer near the bottom of a via formation hole for forming a via. If the conductive film does not adhere stably to the surface of the insulating layer, the power supply becomes insufficient. If the via formation hole is filled with metal by electroplating, defects, such as voids or seams, may be caused in the metal with which the hole is filled. As a result, interlayer connection may be unstable and there is a risk that a failure occurs in the interconnects. If electroplating is not used, the conductive film is not provided stably on the surface of the insulating layer and thus there is a risk that poor conduction is caused in the interlayer connection.